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VHDL程式問題
請問4bit carry look ahead adder 怎麼用VHDL 做出來
最佳解答:
這是教科書最常出的範例，google隨便找也有 關鍵字找 [ 4 bit carry look ahead adder vhdl code ] 就出現一堆: 底下範例是參考 : http://www.openhdl.com/vhdl/647-vhdl-component-4-bit-carry-lookahead-adder.html 還有很多很多很多...慢慢看囉.. LIBRARY ieee;USE ieee.std_logic_1164.all; ENTITY cla_add4 IS PORT ( a : IN STD_LOGIC_VECTOR(3 DOWNTO 0); b : IN STD_LOGIC_VECTOR(3 DOWNTO 0); c_in : IN STD_LOGIC; sum : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); c_out : OUT STD_LOGIC; pg_out : OUT STD_LOGIC; gg_out : OUT STD_LOGIC );END cla_add4; ARCHITECTURE behavioral OF cla_add4 IS SIGNAL P: STD_LOGIC_VECTOR(3 DOWNTO 0); SIGNAL G: STD_LOGIC_VECTOR(3 DOWNTO 0); SIGNAL C: STD_LOGIC_VECTOR(4 DOWNTO 0);BEGIN -- Sum logic sum_prc: PROCESS(a, b, C, c_in) BEGIN sum(0) <= a(0) XOR b(0) XOR c_in; FOR i IN 3 DOWNTO 1 LOOP sum(i) <= a(i) XOR b(i) XOR C(i); END LOOP; END PROCESS; -- Carry-lookahead logic propagate_prc: PROCESS(a, b) BEGIN FOR i IN 3 DOWNTO 0 LOOP P(i) <= a(i) OR b(i); END LOOP; END PROCESS; generate_prc: PROCESS(a, b) BEGIN FOR i IN 3 DOWNTO 0 LOOP G(i) <= a(i) AND b(i); END LOOP; END PROCESS; carry_prc: PROCESS(P, G, C, c_in) BEGIN C(0) <= c_in; FOR i IN 4 DOWNTO 1 LOOP C(i) <= G(i-1) OR (P(i-1) AND C(i-1)); END LOOP; END PROCESS; -- Carry-lookahead output logic c_out <= C(4); pg_out <= P(0) AND P(1) AND P(2) AND P(3); gg_out <= G(3) OR (G(2) AND P(3)) OR (G(1) AND P(3) AND P(2)) OR (G(0) AND P(3) AND P(2) AND P(1)); END behavioral;
其他解答:428DFA428D9FA6F8
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發問:請問4bit carry look ahead adder 怎麼用VHDL 做出來
最佳解答:
這是教科書最常出的範例，google隨便找也有 關鍵字找 [ 4 bit carry look ahead adder vhdl code ] 就出現一堆: 底下範例是參考 : http://www.openhdl.com/vhdl/647-vhdl-component-4-bit-carry-lookahead-adder.html 還有很多很多很多...慢慢看囉.. LIBRARY ieee;USE ieee.std_logic_1164.all; ENTITY cla_add4 IS PORT ( a : IN STD_LOGIC_VECTOR(3 DOWNTO 0); b : IN STD_LOGIC_VECTOR(3 DOWNTO 0); c_in : IN STD_LOGIC; sum : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); c_out : OUT STD_LOGIC; pg_out : OUT STD_LOGIC; gg_out : OUT STD_LOGIC );END cla_add4; ARCHITECTURE behavioral OF cla_add4 IS SIGNAL P: STD_LOGIC_VECTOR(3 DOWNTO 0); SIGNAL G: STD_LOGIC_VECTOR(3 DOWNTO 0); SIGNAL C: STD_LOGIC_VECTOR(4 DOWNTO 0);BEGIN -- Sum logic sum_prc: PROCESS(a, b, C, c_in) BEGIN sum(0) <= a(0) XOR b(0) XOR c_in; FOR i IN 3 DOWNTO 1 LOOP sum(i) <= a(i) XOR b(i) XOR C(i); END LOOP; END PROCESS; -- Carry-lookahead logic propagate_prc: PROCESS(a, b) BEGIN FOR i IN 3 DOWNTO 0 LOOP P(i) <= a(i) OR b(i); END LOOP; END PROCESS; generate_prc: PROCESS(a, b) BEGIN FOR i IN 3 DOWNTO 0 LOOP G(i) <= a(i) AND b(i); END LOOP; END PROCESS; carry_prc: PROCESS(P, G, C, c_in) BEGIN C(0) <= c_in; FOR i IN 4 DOWNTO 1 LOOP C(i) <= G(i-1) OR (P(i-1) AND C(i-1)); END LOOP; END PROCESS; -- Carry-lookahead output logic c_out <= C(4); pg_out <= P(0) AND P(1) AND P(2) AND P(3); gg_out <= G(3) OR (G(2) AND P(3)) OR (G(1) AND P(3) AND P(2)) OR (G(0) AND P(3) AND P(2) AND P(1)); END behavioral;
其他解答:428DFA428D9FA6F8
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